Semiconductor device and method for fabricating the same

ABSTRACT

The invention provides a semiconductor device, including: a substrate; a U-shaped gate dielectric layer formed on the substrate; and a dual work function metal gate layer on the inner surface of U-shaped gate dielectric layer, wherein the dual work function metal gate layer includes a first conductive type metal layer and a second conductive type metal layer.

BACKGROUND OF THE DISCLOSURE

1. Field of the Disclosure

The present disclosure relates to a semiconductor device, and inparticular relates to a semiconductor device having a dual work functionmetal gate and method for fabricating the same.

2. Description of the Related Art

In the course of the semiconductor integrated circuit (IC) evolution,functional density (i.e., the number of interconnected devices per chiparea) has generally increased while geometry size (i.e., the component(or line) that can be created using a fabrication process) hasdecreased.

Specifically, as the dimension of the complementarymetal-oxide-semiconductor (CMOS) devices decreases, short channel effectis increased. Thus, the threshold voltage (V_(th)) of CMOS devices isundesirably reduced.

There are several methods to increase the threshold voltage (V_(th)),such as more channel doping, S/D doping reduction, increase haloimplants, etc. However, the conventional methods have some drawbacks,for example, junction leakage is increased, drain current saturation(IDs) is increased, and junction capacitance is high.

Mid-gap materials having a work function of about 4.6 eV (such as TiN,Ta, W) (near the mid-gap of silicon) may be used as the gate. However,the undesirably gate-induced drain leakage (GIDL) still exists.

Therefore, there is a need to develop a semiconductor device having ahigh threshold voltage (V_(th)) and a low gate-induced drain leakage(GIDL).

BRIEF SUMMARY OF THE DISCLOSURE

The invention provides a semiconductor device, comprising: a substrate;a U-shaped gate dielectric layer formed on the substrate; and a dualwork function metal gate layer on the inner surface of U-shaped gatedielectric layer, wherein the dual work function metal gate layercomprises a first conductive type metal layer and a second conductivetype metal layer.

The invention also provides a method for fabricating a semiconductordevice, comprising: providing a substrate; forming a dummy gate on thesubstrate; forming an inter-layer dielectric layer (ILD) on the dummygate and the substrate; performing a first chemical mechanical polishing(CMP) process to the inter-layer dielectric layer (ILD) to expose anupper surface of the dummy gate; forming a metal layer on the uppersurface of the dummy gate; removing the dummy gate to form a trench inthe inter-layer dielectric layer (ILD); conformally forming a gatedielectric layer in the trench; conformally forming a first conductivetype metal layer on the gate dielectric layer; removing the firstconductive type metal layer and the gate dielectric layer over the metallayer to form a gap in the inter-layer dielectric layer (ILD) and toexpose a portion of the gate dielectric layer; filling a secondconductive type metal layer in the gap, wherein the second conductivetype metal layer is sandwiched between two first conductive type metallayers to form a dual work function metal gate layer; and performing asecond chemical mechanical polishing (CMP) process to the secondconductive type metal layer and the metal layer to expose an uppersurface of the dual work function metal gate layer.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

For a more complete understanding of the present disclosure, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIGS. 1A-1H show cross-sectional schematic representations of variousstages of fabricating a semiconductor device in accordance with anembodiment of the invention.

DETAILED DESCRIPTION OF THE DISCLOSURE

The following description is of the best-contemplated mode of carryingout the disclosure. This description is made for the purpose ofillustrating the general principles of the disclosure and should not betaken in a limiting sense. The scope of the disclosure is bestdetermined by reference to the appended claims.

The invention provides a semiconductor device having a dual workfunction metal gate structure.

FIGS. 1A-1H show cross-sectional schematic representations of variousstages of fabricating a semiconductor device 100 in accordance with anembodiment of the invention.

Referring to FIG. 1A, a substrate 102 is provided, such as a siliconsubstrate. The substrate 102 may alternatively include silicongermanium, gallium arsenic, or other suitable semiconductor materials.The substrate 102 may further include other features such as variousdoped regions, a buried layer, and/or an epitaxy layer. Furthermore, thesubstrate 102 may be a semiconductor on insulator such as silicon oninsulator (SOI). In other embodiments, the semiconductor substrate 102may include a doped epi layer, a gradient semiconductor layer, and/ormay further include a semiconductor layer overlying anothersemiconductor layer of a different type such as a silicon layer on asilicon germanium layer. In other examples, a compound semiconductorsubstrate may include a multilayer silicon structure or a siliconsubstrate may include a multilayer compound semiconductor structure.

Additionally, an isolation structure (not shown) such as a shallowtrench isolation (STI) feature, may be formed in the substrate 102 forisolating an active region in the substrate, as is known in the art. Theisolation structure may be formed of silicon oxide, silicon nitride,silicon oxynitride, fluoride-doped silicate (FSG), and/or a low kdielectric material known in the art.

Then, a dummy gate 104 is formed on the substrate 102. The dummy gate104 may comprise a doped or undoped poly-crystalline silicon (oramorphous silicon), a metal (e.g., tantalum, titanium, molybdenum,tungsten, platinum, aluminum, hafnium, ruthenium), a metal silicide(e.g., titanium silicide, cobalt silicide, nickel silicide, tantalumsilicide), a metal nitride (e.g., titanium nitride, tantalum nitride),other conductive materials or combinations thereof. In an embodiment,the dummy gate 104 is poly-silicon and may be formed by low-pressurechemical vapor deposition.

Next, an inter-layer dielectric layer (ILD layer) 108 is formed on thesubstrate 102 and the dummy gate 104. The inter-layer dielectric layer108 may be formed by atomic layer deposition (ALD), physical vapordeposition (PVD), chemical vapor deposition (CVD), or other acceptablemethods for forming an ILD layer 108. The inter-layer dielectric layer108 may comprise doped or undoped silicon oxide, although othermaterials such as silicon nitride doped silicate glass, high-kmaterials, combinations of these, or the like, may alternatively beutilized.

Additionally, before forming the inter-layer dielectric layer 108, thespacers 106 may be formed on the substrate 102 and a sidewall of thedummy gate 104. The spacers 106 may be formed by blanket depositing oneor more spacer layers (not shown) on the dummy gate 104 and thesubstrate 102. The spacers 106 may comprise SiN, oxynitride, SiC, SiON,oxide, and the like and may be formed by commonly used methods such aschemical vapor deposition (CVD), plasma enhanced CVD, sputter, and othermethods known in the art. Note that in another embodiment, the spacersmay not be formed.

The source/drain regions (not shown in FIG. 1A) may be formed within thesubstrate 102 on opposing sides of the dummy gate 104. Thus, thesource/drain regions may be formed so as to define a channel regionlocated beneath the dummy gate 104.

Referring to FIG. 1A again, a first chemical mechanical polishing (CMP)is performed to the inter-layer dielectric layer (ILD) 108 to expose anupper surface 104 a of the dummy gate 104.

Referring to FIG. 1B, a metal layer 110 is formed on the upper surface104 a of the dummy gate 104. The metal layer 110 may be a p⁺ metal layeror n⁺ metal layer. The metal layer 110 may be formed by atomic layerdeposition (ALD), physical vapor deposition (PVD), chemical vapordeposition (CVD), or other acceptable methods.

In one embodiment, when the semiconductor device is an PMOS device, themetal layer 110 is an n⁺ metal layer. In another embodiment, when thesemiconductor device is NMOS device, the metal layer 110 is a p⁺ metallayer.

Referring to FIG. 1C, the dummy gate 104 is removed to form a trench 120in the inter-layer dielectric layer 108, and the trench 120 has a depthof D1.

Referring to FIG. 1D, a gate dielectric layer 122 is conformally formedin the trench 120. The gate dielectric layer 122 may be formed by atomiclayer deposition (ALD), chemical vapor deposition (CVD), or otheracceptable methods. The gate dielectric layer 122 has a thickness ofabout 5-70 Å, preferably about 5-50 Å.

Additionally, the gate dielectric layer 122 comprises high-k dielectricmaterial, such as HfO₂, ZrO₂, TiO₂, Al₂O₃, HfSiO, HfSiON, HfTaO, HfSiO,HfZrO or combinations thereof.

Referring to FIG. 1E, a first conductive type metal layer 124 isconformally formed on the gate dielectric layer 122. The firstconductive type metal layer 124 may be formed by atomic layer deposition(ALD), chemical vapor deposition (CVD), or other acceptable methods. Thefirst conductive type metal layer 124 has a thickness of about 4-20 nm,preferably about 4-10 nm.

In one embodiment, when the semiconductor device is a PMOS device, thefirst conductive type metal layer 124 is an n⁺ metal layer.

In another embodiment, when the semiconductor device is NMOS device, thefirst conductive type metal layer 124 is a p⁺ metal layer.

The n⁺ metal layer has a work function of about 4.1-4.9 and comprisesscandium (Sc), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium,(Ti), tantalum (Ta) or niobium (Nb).

The p⁺ metal layer has a work function of about 4.7-5.0 and comprisestungsten (W), platinum (Pt), ruthenium (Ru), molybdenum (Mo), titaniumrbide (TiC), zirconium arbide (ZrC), tantalum carbide (TaC), tungstencarbide (WC), titanium nitride (TiN), tantalum nitride (TaN) orruthenium oxide (RuO).

Referring to FIG. 1E, the first conductive type metal layer 124 and thegate dielectric layer 122 over the metal layer 110 is removed to form agap 125 in the inter-layer dielectric layer 108 and to expose a portionof the gate dielectric layer 122.

Note that after the above removing step, the gate dielectric layer 122has a U-shaped structure, and the U-shaped gate dielectric layer 122comprises a horizontal portion 122 a and two vertical portions 122 b,and the two vertical portions 122 b are located at opposite ends of thehorizontal portion 122 a. Two first conductive type metal layers 124 areadjacent to the vertical portions 122 b of the U-shaped gate dielectriclayer 122.

An etching process such as a dry etching technique (e.g., anisotropicetching) may be performed on the first conductivity type metal layer 124such that a portion of the first conductivity type metal layer 124remains on the sidewalls of horizontal portion 122 a of the U-shapedgate dielectric layer 122.

The gap 125 has a width of D2, and the D1 of the trench 120 is largerthan D2 of the gap 125.

Referring to FIG. 1G, a second conductive type metal layer 126 is filledin the gap 125, and thus the second conductive type metal layer 126 issandwiched between two first conductive type metal layers 124 to form adual work function metal gate layer 130.

In one embodiment, when the semiconductor device is a PMOS device, thefirst conductive type metal layer 124 is an n⁺ metal layer, and thesecond conductive type metal layer 126 is a p⁺ metal layer.

In another embodiment, when the semiconductor device is an NMOS device,the first conductive type metal layer 124 is a p⁺ metal layer, and thesecond conductive type metal layer 126 is an n⁺ metal layer.

Referring to FIG. 1H, a second chemical mechanical polishing (CMP) isperformed to the second conductive type metal layer 126 and the metallayer 110 to expose an upper surface of the dual work function metalgate layer 130. Thus, a semiconductor device 100 having the dual workfunction metal gate layer 130 is formed by the above-mentioned steps.

As shown in FIG. 1H, the invention also provides a semiconductor device100 which comprises: a substrate 102; a U-shaped gate dielectric layer122 formed on the substrate 102; and a dual work function metal gatelayer 130 on the inner surface of U-shaped gate dielectric layer 122,wherein the dual work function metal gate layer 130 comprises a firstconductive type metal layer 124 and a second conductive type metal layer126.

The U-shaped gate dielectric layer 122 comprises a horizontal portion122 a and two vertical portions 122 b, and the two vertical portions 122b are located at opposite ends of the horizontal portion 122 a.Additionally, the dual work function metal gate layer 130 comprises twofirst conductive type metal layers 124 adjacent to the vertical portions122 b of the U-shaped gate dielectric layer 122 and the secondconductive type metal layer 126 sandwiched between two first conductivetype metal layers 124.

For example, when the semiconductor device is a PMOS device, the firstconductive type metal layer 124 is an n⁺ metal layer, and the secondconductive type metal layer 126 is a p⁺ metal layer. In other words, thep⁺ metal layer sandwiched between two n⁺ metal layers. Because themiddle p⁺ metal layer has a higher work function, the dual work functionmetal gate layer 130 has a higher threshold voltage (V_(th)) for thep-channel below the middle p⁺ metal layer. Because the n+ metal layerhas a lower work function, the undesirably gate-induced drain leakage(GIDL) between the n+ metal layer and the drain (not shown in figures)is reduced.

From the above description, compared with the single work function metalgate in prior art, due to the dual work function metal gate layer of theinvention having two different work functions, the threshold voltage(Vth) is increased and the gate-induced drain leakage (GIDL) is reduced.

While the disclosure has been described by way of example and in termsof the preferred embodiments, it is to be understood that the disclosureis not limited to the disclosed embodiments. To the contrary, it isintended to cover various modifications and similar arrangements (aswould be apparent to those skilled in the art). Therefore, the scope ofthe appended claims should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

What is claimed is:
 1. A semiconductor device, comprising: a substrate;a U-shaped gate dielectric layer formed on the substrate; and a dualwork function metal gate layer on the inner surface of U-shaped gatedielectric layer, wherein the dual work function metal gate layercomprises a first conductive type metal layer and a second conductivetype metal layer.
 2. The semiconductor device as claimed in claim 1,wherein the U-shaped gate dielectric layer comprises a horizontalportion and two vertical portions, and the two vertical portions arelocated at opposite ends of the horizontal portion.
 3. The semiconductordevice as claimed in claim 2, wherein the dual work function metal gatelayer comprises: two first conductive type metal layers adjacent to thevertical portions of the U-shaped gate dielectric layer; and the secondconductive type metal layer sandwiched between two first conductive typemetal layers.
 4. The semiconductor device as claimed in claim 1, whereinthe first conductive type metal layer is a p⁺ metal layer and the secondconductive type metal layer is an n⁺ metal layer.
 5. The semiconductordevice as claimed in claim 1, wherein the first conductive type metallayer is an n⁺ metal layer and the second conductive type metal layer isa p⁺ metal layer.
 6. The semiconductor device as claimed in claim 1,wherein the n⁺ metal layer has a work function of about 4.1-4.9.
 7. Thesemiconductor device as claimed in claim 5, wherein the n⁺ metal layercomprises scandium (Sc), zirconium (Zr), hafnium (Hf), aluminum (Al),titanium, (Ti), tantalum (Ta) or niobium (Nb).
 8. The semiconductordevice as claimed in claim 5, wherein the p⁺ metal layer has a workfunction of about 4.7-5.0.
 9. The semiconductor device as claimed inclaim 5, wherein the p⁺ metal layer comprises tungsten (W), platinum(Pt), ruthenium (Ru), molybdenum (Mo), titanium carbide (TiC), zirconiumarbide (ZrC), tantalum carbide (TaC), tungsten carbide (WC), titaniumnitride (TiN), tantalum nitride (TaN) or ruthenium oxide (RuO).
 10. Thesemiconductor device as claimed in claim 1, wherein the U-shaped gatedielectric layer comprises high-k dielectric material.
 11. Thesemiconductor device as claimed in claim 10, wherein the high-kdielectric material comprises HfO₂, ZrO₂, TiO₂, Al₂O₃, HfSiO, HfSiON,HfTaO, HfSiO, HfZrO or combinations thereof.
 12. The semiconductordevice as claimed in claim 1, further comprising: an inter-layerdielectric layer (ILD) formed on the substrate and on a sidewall of thedual work function metal gate layer.
 13. The semiconductor device asclaimed in claim 12, further comprising: a spacer formed on thesubstrate, wherein the spacer is formed between the inter-layerdielectric layer (ILD) and the dual work function metal gate layer. 14.A method for fabricating a semiconductor device, comprising: providing asubstrate; forming a dummy gate on the substrate; forming an inter-layerdielectric layer (ILD) on the dummy gate and the substrate; performing afirst chemical mechanical polishing (CMP) process to the inter-layerdielectric layer (ILD) to expose an upper surface of the dummy gate;forming a metal layer on the upper surface of the dummy gate; removingthe dummy gate to form a trench in the inter-layer dielectric layer(ILD); conformally forming a gate dielectric layer in the trench;conformally forming a first conductive type metal layer on the gatedielectric layer; removing the first conductive type metal layer and thegate dielectric layer over the metal layer to form a gap in theinter-layer dielectric layer (ILD) and to expose a portion of the gatedielectric layer; filling a second conductive type metal layer in thegap, wherein the second conductive type metal layer is sandwichedbetween two first conductive type metal layers to form a dual workfunction metal gate layer; and performing a second chemical mechanicalpolishing (CMP) process to the second conductive type metal layer andthe metal layer to expose an upper surface of the dual work functionmetal gate layer.
 15. The method for fabricating a semiconductor deviceas claimed in claim 14, before forming the inter-layer dielectric layer(ILD) on the dummy gate and the substrate, further comprising: forming aspacer on a sidewall of the dummy gate.
 16. The method for fabricating asemiconductor device as claimed in claim 14, wherein the metal layercomprises p⁺ metal layer or n⁺ metal layer.
 17. The method forfabricating a semiconductor device as claimed in claim 14, afterremoving the first conductive type metal layer and the gate dielectriclayer over the metal layer, wherein the gate dielectric layer has aU-shaped structure, and the U-shaped gate dielectric layer comprises ahorizontal portion and two vertical portions, and the two verticalportions are located at opposite ends of the horizontal portion.
 18. Themethod for fabricating a semiconductor device as claimed in claim 17,wherein two first conductive type metal layers are adjacent to thevertical portions of the U-shaped gate dielectric layer.
 19. The methodfor fabricating a semiconductor device as claimed in claim 14, whereinthe gate dielectric layer comprises high-k dielectric material.
 20. Themethod for fabricating a semiconductor device as claimed in claim 14,wherein the first conductive type metal layer is a p⁺ metal layer andthe second conductive type metal layer is an n⁺ metal layer.
 21. Themethod for fabricating a semiconductor device as claimed in claim 14,wherein the first conductive type metal layer is an n⁺ metal layer andthe second conductive type metal layer is a p⁺ metal layer.
 22. Themethod for fabricating a semiconductor device as claimed in claim 14,wherein a width of the trench is larger than that of the gap.